High Impedance Differential Clock Divider

Product Overview


The ASP-DCD-00 board is a high impedance input clock divider circuit. It is designed to provide minimum load to a clock source for frequency measurement. It accept single ended (Unbalanced) or differential (Balanced) signals with amplitudes as little as 100mV rms; it divides the input signal frequency from 2 to 256 times depending on shunt jumper selections on J3. The board requires 5VDC 500mA power source to operate. The output is capable of driving 5V TTL logic levels.

Hardware Specifications

  • Model part number: ASP-DCD-00 rev A.0
  • Input frequency: 10 KHz – 150 MHz
  • Input impedance: 100 KOhm
  • Input Voltage: 100mv RMS (280mv PK – PK) to 1.16v RMS (3.3v PK – PK)
  • Output Impedance: 100 Ohm
  • Output Voltage: 5V TTL
  • Power supply voltage: 4.85 – 5.15 V
  • Power supply current: 500 mA (Max)
  • Clock divider divisions: ÷2, ÷4, ÷8, ÷16, ÷32, ÷64, ÷128, ÷256
  • Physical dimension: 3” x 0.75” (7.6 cm x 1.9 cm)

Differential Clock Divider User Manual.

Differential Clock Divider Mechanical Drawing (DXF)

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Unit Price: $325